Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7175
-gerrit
commit d98f537f490bf779fef0ec1fa9484060e8166e62 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Fri Oct 24 01:34:25 2014 +1100
bd82x6x/sata: Fix AHCI mode bits for max port split between controllers
According to the Intel datasheet under 'MAP - Address Map Register (SATA-D31:F2)', 2 flags, SATA Mode Select (SMS) and SATA Port-to-Controller Configuration (SC), must be set when in AHCI mode.
Other bits [4:0], [15:8] and under the special condition of '0b11' in [7:6] within this register are marked as reserved and so do a read and mask before writing over them.
Make 'devicetree' configurable the alternative possible six port map splitting possible between the first and second controllers via the boolean 'sata_port_split' as configurable in bit 5. Possible splits are 2/4 and 6/0 with a default of 6/0.
Note that bit 5 should be '1' while in AHCI/RAID mode.
Change-Id: I7872f0d4d4ffacbf4f80bb0157389ed8593d42e9 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com Co-Author: Damien Zammit damien@zamaudio.com --- src/southbridge/intel/bd82x6x/chip.h | 1 + src/southbridge/intel/bd82x6x/sata.c | 12 +++++++++++- 2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 0f2f0e9..e8d1da9 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -65,6 +65,7 @@ struct southbridge_intel_bd82x6x_config {
/* IDE configuration */ uint8_t sata_port_map; + uint8_t sata_port_split; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx;
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index cb5699e..b577ba2 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -224,15 +224,25 @@ static void sata_enable(device_t dev) if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) sata_mode = 0;
+ /* Take care with map as 0x90 has reserved bits */ + map = pci_read_config16(dev, 0x90); + /* * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ if (sata_mode == 0) - map = 0x0060; + map |= 0x0060;
map |= (config->sata_port_map ^ 0x3f) << 8;
+ /* Toggle between 6/0 or 2/4 split first/second respective + * controllers where: + * 2/4 is configured by sata_port_split = 0 + * 6/0 is configured by sata_port_split = 1 + */ + map |= (config->sata_port_split << 5) & 0x20; + pci_write_config16(dev, 0x90, map); }