[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: add soc implementation for ETR address API

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37555 )

Change subject: soc/intel/tigerlake: add soc implementation for ETR address API
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soc/intel/tigerlake: add soc implementation for ETR address API

Add soc implementation for the new ETR address API.

Change-Id: Icc471b16304c72a9341abdd9797ba3f8d0d3d1bc
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/tigerlake/pmutil.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/37555/1

diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c
index 53f8609..c163dc2 100644
--- a/src/soc/intel/tigerlake/pmutil.c
+++ b/src/soc/intel/tigerlake/pmutil.c
@@ -177,6 +177,12 @@
    return (uintptr_t)pmc_mmio_regs();
 }

+
+uint32_t *soc_pmc_etr_addr(void)
+{
+	return (uint32_t *)(soc_read_pmc_base() + ETR);
+}
+
 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 {
    DEVTREE_CONST struct soc_intel_tigerlake_config *config;