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Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79025?usp=email )
Change subject: [RFC] nb/intel/haswell: Allow specifying SPD addresses in devicetree ......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
I'm not sure if the potential for confusion (SPD addresses can be specified in two different places, […]
Following this line of thought, have I gone too far with sandybridge?
An earlier iteration was exactly the Haswell approach, but during review some devs called for SPD addresses in devicetree for boards without SPD in CBFS (which is the majority) when I proposed to drop that pre-existing (but unused) setting and go full Haswell. Boilerplate reduction I guess. We all know with memory down there is no avoiding runtime code.