Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Nico Huber, Subrata Banik.
Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81638?usp=email )
Change subject: intel/alderlake: Add helper functions for Power Management ......................................................................
Patch Set 4:
(3 comments)
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/81638/comment/9c2163b9_726d5e43 : PS4, Line 799: };
Why are these declared separately? How should a mainboard dev know where to use them? […]
My theory was this patch, hook it up to the option API, move to common code, tidy the enums - just did this one to start with as I didn't expect it to land as ASPM has had reverts for ADL before
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/81638/comment/f118ece0_3c3d97ab : PS4, Line 504: default "auto"
I assume you are referring to the value in the FSP binary? That's generally […]
Right, so if someone (google) uses a modified version of FSP, shouldn't they add a quirk?
https://review.coreboot.org/c/coreboot/+/81638/comment/0d15ba99_5be5a63c : PS4, Line 506: s_cfg->PcieRpAspm[index] = rp_cfg->pcie_rp_aspm;
These usually aren't compatible, because coreboot values are off-by-1 to allow […]
`> 0`?