[coreboot-gerrit] Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37168 )

Change subject: sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization
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Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37168/9/src/southbridge/amd/agesa/h... 
File src/southbridge/amd/agesa/hudson/early_setup.c:

https://review.coreboot.org/c/coreboot/+/37168/9/src/southbridge/amd/agesa/h... 
PS9, Line 97: 	tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2
> This might look better with shorter macro names. […]

I agree. Now that I think of this more, I think common bootblock should only open up the serial port IO and 2e/4e routes to LPC. I am not so eager to use devicetree here, while I know Intel side generally does it now.