Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32376 )
Change subject: superio/fintek/f71808a: Add more optional ramstage registers ......................................................................
Patch Set 2:
(1 comment)
only had a very brief look at the patch
https://review.coreboot.org/#/c/32376/2/src/superio/fintek/f71808a/f71808a_m... File src/superio/fintek/f71808a/f71808a_multifunc.c:
https://review.coreboot.org/#/c/32376/2/src/superio/fintek/f71808a/f71808a_m... PS2, Line 36: : if (conf->configuration_port_select_0x27) { : pnp_write_config(dev, CONFIGURATION_PORT_SELECT, : conf->configuration_port_select_0x27); : } This smells like a recipe for disaster to me. Changing the SIO config interface base address (I haven't seen a board where this was needed) will likely break SIO access and the other case would be that the change would never be applied to the SIO. So I don't see a reason to write the PORT_4E_EN bit. If your intention is to just make PWOK_MODE configurable, then only change that bit instead of the full register.