Gabe Black (gabeblack@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3693
-gerrit
commit 45dfe231642ca2b5069a9e2018106266d50621f3 Author: Ronald G. Minnich rminnich@google.com Date: Wed Jun 19 15:46:25 2013 -0700
Exynos5420: add code to make sure resume will work on DRAM.
Found during a perusal of u-boot changes. It looks important. For more info: http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commit...
Change-Id: Ida2fe2a98be008a4bdfe594cf00d01a33b511b4f Signed-off-by: Ronald G. Minnich rminnich@google.com Signed-off-by: Gabe Black gabeblack@chromium.org --- src/cpu/samsung/exynos5420/bootblock.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/src/cpu/samsung/exynos5420/bootblock.c b/src/cpu/samsung/exynos5420/bootblock.c index d3d737e..5cc9ef6 100644 --- a/src/cpu/samsung/exynos5420/bootblock.c +++ b/src/cpu/samsung/exynos5420/bootblock.c @@ -19,10 +19,28 @@
#include "clk.h" #include "wakeup.h" +#include "cpu.h"
void bootblock_cpu_init(void); void bootblock_cpu_init(void) { + u32 ret; + /* + * During Suspend-Resume & S/W-Reset, as soon as PMU releases + * pad retention, CKE goes high. This causes memory contents + * not to be retained during DRAM initialization. Therfore, + * there is a new control register(0x100431e8[28]) which lets us + * release pad retention and retain the memory content until the + * initialization is complete. + */ + if (read32(((void *)INF_REG_BASE + INF_REG1_OFFSET)) == S5P_CHECK_SLEEP) { + write32(PAD_RETENTION_DRAM_COREBLK_VAL, + (void *)PAD_RETENTION_DRAM_COREBLK_OPTION); + do { + ret = read32((void *)PAD_RETENTION_DRAM_STATUS); + } while (ret != 0x1); + } + /* kick off the multi-core timer. * We want to do this as early as we can. */