[coreboot-gerrit] Change in coreboot[master]: vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake

[Srinidhi N Kaushik (Code Review)]

Attention is currently required from: Ravishankar Sarawadi, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph.
Hello build bot (Jenkins), Furquan Shaikh, Ravishankar Sarawadi, Tim Wawrzynczak, Nick Vaccaro, Raj Astekar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/54811

to look at the new patch set (#2).

Change subject: vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake
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vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake

Update FSP headers for Tiger Lake platform generated based on FSP
version 4133 to include post PRQ UPDs.

BUG=b:188452018
BRANCH=none
TEST=build voxel

Signed-off-by: Srinidhi N Kaushik 
Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6
---
M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
2 files changed, 2,138 insertions(+), 201 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/54811/2