[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Set missing RTC offsets for day alarm and century

[Anand K Mistry (Code Review)]

Anand K Mistry has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55001 )

Change subject: soc/amd/stoneyridge: Set missing RTC offsets for day alarm and century
......................................................................

soc/amd/stoneyridge: Set missing RTC offsets for day alarm and century

The RTC Date Alarm and RTC AltCentury fields are supported on
Stoneyridge.

This is a mirror of commit 041fcf59025bb1801828441e09b2f56b48e12fdc made
for picasso.

BUG=b:187516317
TEST=On a Chrome OS 'grunt' device, run
     `time powerd_dbus_suspend --suspend_for_sec=172800`
     and verify the system suspended and woke up after 48 hours

Signed-off-by: Anand K Mistry 
Change-Id: I10831b982662e680fa71aa81d02935e1b7e7a7a1
---
M src/soc/amd/stoneyridge/acpi.c
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/55001/1

diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index de79ec3..307db8b 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -82,9 +82,9 @@
    fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
    fadt->duty_offset = 1;	/* CLK_VAL bits 3:1 */
    fadt->duty_width = 3;	/* CLK_VAL bits 3:1 */
-	fadt->day_alrm = 0;	/* 0x7d these have to be */
-	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
-	fadt->century = 0;	/* 0x7f to make rtc alarm work */
+	fadt->day_alrm = 0x0d;
+	fadt->mon_alrm = 0;
+	fadt->century = 0x32;
    fadt->iapc_boot_arch = FADT_BOOT_ARCH;	/* See table 5-10 */
    fadt->res2 = 0;		/* reserved, MUST be 0 ACPI 3.0 */
    fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */