Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13658
-gerrit
commit dac6c27a70bcd32a5537d03f146f611bdfb06332 Author: Vladimir Serbinenko phcoder@gmail.com Date: Wed Feb 10 02:36:04 2016 +0100
Make MRC vs native a config rather than making a separate chipset for it.
Tested by making lenovo x230 configurable despite pretty MRC bugs.
Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7 Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/Kconfig | 7 +++--- src/cpu/intel/Makefile.inc | 2 -- src/mainboard/apple/macbookair4_2/Kconfig | 1 + src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 1 + src/mainboard/gigabyte/ga-b75m-d3v/Kconfig | 1 + src/mainboard/google/butterfly/Kconfig | 1 + src/mainboard/google/link/Kconfig | 6 +++++- src/mainboard/google/parrot/Kconfig | 2 +- src/mainboard/google/parrot/devicetree.cb | 2 ++ src/mainboard/google/parrot/romstage.c | 25 +++++++++++++++++++++ src/mainboard/google/stout/Kconfig | 6 +++++- src/mainboard/intel/emeraldlake2/Kconfig | 6 +++++- src/mainboard/kontron/ktqm77/Kconfig | 6 +++++- src/mainboard/lenovo/t420s/Kconfig | 1 + src/mainboard/lenovo/t430s/Kconfig | 1 + src/mainboard/lenovo/t520/Kconfig | 1 + src/mainboard/lenovo/t530/Kconfig | 1 + src/mainboard/lenovo/x220/Kconfig | 1 + src/mainboard/lenovo/x230/Kconfig | 1 + src/mainboard/samsung/lumpy/Kconfig | 6 +++++- src/mainboard/samsung/stumpy/Kconfig | 6 +++++- src/northbridge/intel/sandybridge/Kconfig | 30 ++++++++++---------------- src/northbridge/intel/sandybridge/Makefile.inc | 14 ++++++------ src/northbridge/intel/sandybridge/romstage.c | 3 +-- src/southbridge/intel/bd82x6x/Makefile.inc | 9 ++++---- src/southbridge/intel/bd82x6x/usb_ehci.c | 4 ++-- util/autoport/sandybridge.go | 1 + util/board_status/to-wiki/towiki.sh | 4 ++-- 28 files changed, 100 insertions(+), 49 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig index 35acad4..fdc4dff 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -253,8 +253,8 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config FLASHMAP_OFFSET hex "Flash Map Offset" - default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC - default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE_MRC + default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE + default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE default CBFS_SIZE if !ARCH_X86 default 0 help @@ -380,8 +380,7 @@ config CBFS_SIZE hex "Size of CBFS filesystem in ROM" default 0x100000 if HAVE_INTEL_FIRMWARE || \ NORTHBRIDGE_INTEL_X4X || \ - NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || \ - NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || \ + NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_IVYBRIDGE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BRASWELL || \ SOC_INTEL_BROADWELL diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 1234588..bd39039 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -20,9 +20,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370 subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA988B) += socket_rPGA988B subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE) += fsp_model_206ax diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index 6e47a7b..c919481 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_EDID select INTEL_INT15 select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT select SANDYBRIDGE_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index 8a53bef..7ca0b5d 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS select ARCH_X86 select CPU_INTEL_SOCKET_LGA1155 select NORTHBRIDGE_INTEL_IVYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select SUPERIO_ITE_IT8728F select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig index ede8021..3caf155 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS select ARCH_X86 select CPU_INTEL_SOCKET_LGA1155 select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select SUPERIO_ITE_IT8728F select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 320981a..1fc9c0a 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_ENE_KB3940Q select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 2d9a9de..c9bfa2e 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC + select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC @@ -16,6 +16,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT
+config USE_NATIVE_RAMINIT + bool + default n + config CHROMEOS select CHROMEOS_VBNV_CMOS select LID_SWITCH diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index e9b55a4..56ebf86 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC + select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_COMPAL_ENE932 select BOARD_ROMSIZE_KB_8192 diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 0a54566..eacfe57 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -18,6 +18,8 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x000001d4" register "gpu_pch_backlight" = "0x03aa0000"
+ register "max_mem_clock_mhz" = "666" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 030f7c4..5897d13 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -28,6 +28,7 @@ #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> @@ -158,6 +159,30 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) *pei_data = pei_data_template; }
+const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled power usb oc pin */ + { 0, 0, -1 }, /* P0: Empty */ + { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ + { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ + { 1, 0, 1 }, /* P3: Left USB 3 (OC1) */ + { 0, 0, -1 }, /* P4: Empty */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ + { 1, 0, -1 }, /* P8: MiniPCIe (WLAN) (no OC) */ + { 0, 0, -1 }, /* P9: Empty */ + { 1, 0, -1 }, /* P10: Camera (no OC) */ + { 0, 0, -1 }, /* P11: Empty */ + { 0, 0, -1 }, /* P12: Empty */ + { 0, 0, -1 }, /* P13: Empty */ +}; + +void mainboard_get_spd(spd_raw_data *spd) { + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); +} + void mainboard_config_superio(void) { } diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 94229c4..9dc2649 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC + select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_IT8518 select BOARD_ROMSIZE_KB_8192 @@ -16,6 +16,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_LPC_TPM select INTEL_INT15
+config USE_NATIVE_RAMINIT + bool + default n + config CHROMEOS select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 1d63e76..ae233ab 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -3,7 +3,7 @@ if BOARD_INTEL_EMERALDLAKE2 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC + select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select SUPERIO_SMSC_SIO1007 select BOARD_ROMSIZE_KB_8192 @@ -13,6 +13,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 #select MAINBOARD_HAS_CHROMEOS
+config USE_NATIVE_RAMINIT + bool + default n + config CHROMEOS #select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index 9dc75cc..ba5e3da 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -3,7 +3,7 @@ if BOARD_KONTRON_KTQM77 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC + select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select SUPERIO_WINBOND_W83627DHG select EC_KONTRON_IT8516E @@ -14,6 +14,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ENABLE_VMX select HAVE_MRC
+config USE_NATIVE_RAMINIT + bool + default n + config MAINBOARD_DIR string default kontron/ktqm77 diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 65d37a7..27b3afc 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA988B select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 6e257dd..000b156 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index df7c2db..edf2868 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA988B select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 7b4ca7a..427794b 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 02b9873..b7c49aa 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 1d336eb..2078cf0 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE + select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index ac19be5..d0f3844 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_SMSC_MEC1308 # LPC47N207 selected for external LPC card @@ -21,6 +21,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select HAVE_MRC
+config USE_NATIVE_RAMINIT + bool + default n + config CHROMEOS select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index d4b8cc2..50b1625 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC + select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_ITE_IT8772F # LPC47N207 selected for external LPC card @@ -18,6 +18,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MRC select INTEL_INT15
+config USE_NATIVE_RAMINIT + bool + default n + config CHROMEOS select PHYSICAL_REC_SWITCH select CHROMEOS_VBNV_CMOS diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 3e517b1..fd5e0a1 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -13,12 +13,6 @@ ## GNU General Public License for more details. ##
-config NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC - bool - select MMCONF_SUPPORT - select MMCONF_SUPPORT_DEFAULT - select CPU_INTEL_MODEL_206AX - select INTEL_GMA_ACPI
config NORTHBRIDGE_INTEL_SANDYBRIDGE bool @@ -28,13 +22,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI
-config NORTHBRIDGE_INTEL_IVYBRIDGE_MRC - bool - select MMCONF_SUPPORT - select MMCONF_SUPPORT_DEFAULT - select CPU_INTEL_MODEL_306AX - select INTEL_GMA_ACPI - config NORTHBRIDGE_INTEL_IVYBRIDGE bool select MMCONF_SUPPORT @@ -43,7 +30,14 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI
-if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE +if NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE + +config USE_NATIVE_RAMINIT + bool "Use native raminit" + default y + help + Select if you want to use coreboot implementation of raminit rather than + System Agent/MRC.bin. You should answer Y.
config VGA_BIOS_ID string @@ -68,10 +62,8 @@ config MRC_CACHE_SIZE
config DCACHE_RAM_BASE hex - default 0xff7e0000 if NORTHBRIDGE_INTEL_IVYBRIDGE_MRC - default 0xff7e0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC - default 0xfefe0000 if NORTHBRIDGE_INTEL_IVYBRIDGE - default 0xfefe0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE + default 0xff7e0000 if !USE_NATIVE_RAMINIT + default 0xfefe0000 if USE_NATIVE_RAMINIT
config DCACHE_RAM_SIZE hex @@ -87,7 +79,7 @@ config DCACHE_RAM_MRC_VAR_SIZE
config HAVE_MRC bool "Add a System Agent binary" - depends on !NORTHBRIDGE_INTEL_IVYBRIDGE && !NORTHBRIDGE_INTEL_SANDYBRIDGE + depends on !USE_NATIVE_RAMINIT help Select this option to add a System Agent binary to the resulting coreboot image. diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 90abe4d..7a3c498 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -13,7 +13,7 @@ # GNU General Public License for more details. #
-ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC),y) +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE)$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE),y)
ramstage-y += ram_calc.c ramstage-y += northbridge.c @@ -25,12 +25,12 @@ ramstage-y += acpi.c ramstage-y += mrccache.c
romstage-y += ram_calc.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += raminit_mrc.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC) += raminit_mrc.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += raminit.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ../../../device/dram/ddr3.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += raminit.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ../../../device/dram/ddr3.c +ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) +romstage-y += raminit.c +romstage-y += ../../../device/dram/ddr3.c +else +romstage-y += raminit_mrc.c +endif romstage-y += romstage.c romstage-y += mrccache.c romstage-y += iommu.c diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 04db608..7b367c5 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -70,8 +70,7 @@ void main(unsigned long bist) mainboard_config_superio();
/* USB is inited in MRC if MRC is used. */ - if (!(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC - || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC)) { + if (CONFIG_USE_NATIVE_RAMINIT) { early_usb_init(mainboard_usb_ports); }
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index a8dd7be..c85151c 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -46,10 +46,11 @@ romstage-y += reset.c romstage-y += early_spi.c early_pch_common.c romstage-y += early_rcba.c
-romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_MRC) += early_me_mrc.c early_usb_mrc.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC) += early_me_mrc.c early_usb_mrc.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_thermal.c early_pch.c early_me.c early_usb.c -romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_thermal.c early_pch.c early_me.c early_usb.c +ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) +romstage-y += early_thermal.c early_pch.c early_me.c early_usb.c +else +romstage-y += early_me_mrc.c early_usb_mrc.c +endif
ramstage-y += madt.c
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index b7cd5f0..c0cb1a9 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -35,7 +35,7 @@ static void usb_ehci_init(struct device *dev) printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
/* For others, done in MRC. */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) +#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) pci_write_config32(dev, 0x84, 0x930c8811); pci_write_config32(dev, 0x88, 0x24000d30); pci_write_config32(dev, 0xf4, 0x80408588); @@ -50,7 +50,7 @@ static void usb_ehci_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32);
/* For others, done in MRC. */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) +#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) struct resource *res; u8 access_cntl;
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 191c69f..080cc23 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -119,6 +119,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { KconfigBool["INTEL_EDID"] = true KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE"] = true + KconfigBool["USE_NATIVE_RAMINIT"] = true KconfigBool["INTEL_INT15"] = true KconfigBool["HAVE_ACPI_TABLES"] = true KconfigBool["HAVE_ACPI_RESUME"] = true diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 922e470..85334ef 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -326,9 +326,9 @@ EOF case $northbridge in INTEL_HASWELL) cpu_nice="Intel® 4th Gen (Haswell) Core i3/i5/i7";; - INTEL_IVYBRIDGE|INTEL_IVYBRIDGE_MRC|INTEL_FSP_IVYBRIDGE) + INTEL_IVYBRIDGE|INTEL_FSP_IVYBRIDGE) cpu_nice="Intel® 3rd Gen (Ivybridge) Core i3/i5/i7";; - INTEL_SANDYBRIDGE|INTEL_SANDYBRIDGE_MRC) + INTEL_SANDYBRIDGE) cpu_nice="Intel® 2nd Gen (Sandybridge) Core i3/i5/i7";; *) cpu_nice="$northbridge";;