[coreboot-gerrit] Change in ...coreboot[master]: intel/lynxpoint: Fix spelling

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30687

Change subject: intel/lynxpoint: Fix spelling
......................................................................

intel/lynxpoint: Fix spelling

Change-Id: I684e1962a9d4312ee9fad4ada70323b02ca3ae48
Signed-off-by: Kyösti Mälkki 
---
M src/southbridge/intel/lynxpoint/bootblock.c
M src/southbridge/intel/lynxpoint/lpc.c
2 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/30687/1

diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 20d0ee3..1a9e7bb 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -54,7 +54,7 @@

static void enable_port80_on_lpc(void)
 {
-	/* Enable port 80 POST on LPC. The chipset does this by deafult,
+	/* Enable port 80 POST on LPC. The chipset does this by default,
     * but it doesn't appear to hurt anything. */
    u32 gcs = RCBA32(GCS);
    gcs = gcs & ~0x4;
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 5b48da0..2738f3a 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -660,7 +660,7 @@
 {
    /*
     * Check if the register is enabled. If so and the base exceeds the
-	 * device's deafult claim range add the resoure.
+	 * device's default, claim range and add the resource.
     */
    if (reg_value & 1) {
    	u16 base = reg_value & 0xfffc;