[coreboot-gerrit] Change in coreboot[master]: sb/amd/sb800: Remove bit shift that does nothing

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34395 )

Change subject: sb/amd/sb800: Remove bit shift that does nothing
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sb/amd/sb800: Remove bit shift that does nothing

This bit shift attempts to set bits 8 and 9 of the byte variable (counting
from 0). However, as the name suggests, this variable is only 8 bits
wide, so the shift does nothing. Reading section 7.5 of the
AMD SB800-Series Southbridges Register Programming Requirements manual,
bits 8 and 9 are already set by default, so we can remove the bit shift.
(Alternatively, we could try setting the corresponding bits one byte
higher in 0xF1 if needed.)

Change-Id: I645236441e02925ee01339378d213cb343027363
Signed-off-by: Jacob Garber 
Found-by: Coverity CID 1229582
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34395
Tested-by: build bot (Jenkins) 
Reviewed-by: Kyösti Mälkki 
---
M src/southbridge/amd/sb800/usb.c
1 file changed, 0 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Kyösti Mälkki: Looks good to me, approved

diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c
index bc8c1c6..063750d 100644
--- a/src/southbridge/amd/sb800/usb.c
+++ b/src/southbridge/amd/sb800/usb.c
@@ -42,7 +42,6 @@
    /* RPR 7.4 Enable the USB controller to get reset by any software that generate a PCIRst# condition */
    byte = pm_ioread(0xF0);
    byte |= (1 << 2);
-	byte |= 3 << 8;		/* rpr 7.5 */
    pm_iowrite(0xF0, byte);

/* RPR 7.9 Disable OHCI MSI Capability. */