Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45378 )
Change subject: nb/intel/ironlake: Drop casts from DEFAULT_{MCHBAR,DMIBAR} ......................................................................
nb/intel/ironlake: Drop casts from DEFAULT_{MCHBAR,DMIBAR}
This allows dropping some casts. Changes the binary, though.
Change-Id: Icff7919f7321a08338db2f0a765ebd605fd00ae2 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/ironlake.h 2 files changed, 2 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45378/1
diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index fa89bd9..e0120fe 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -19,9 +19,9 @@ /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, 0); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, 0); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0);
/* Set C0000-FFFFF to access RAM on both reads and writes */ diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index aa9a8b7..9faa661 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -26,13 +26,8 @@ #define IRONLAKE_SERVER 2
/* Northbridge BARs */ -#ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ -#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ -#else #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#define QUICKPATH_BUS 0xff