[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Fix final MTRR usage

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47868 )

Change subject: soc/intel/xeon_sp: Fix final MTRR usage
......................................................................

soc/intel/xeon_sp: Fix final MTRR usage

The region top_of_ram -> cbmem_top is used by FSP, but is also just
regular DRAM. Marking it as such improves the final MTRR solution a
lot and fixes MTRR starvation depending on the setup.

Change-Id: I19ff7cf2d699b4cc34caccd91cafd6a284d699d3
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/47868/1

diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 15a9f0f..94aabab 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -182,6 +182,11 @@
    LOG_MEM_RESOURCE("low_ram", dev, index, base_kb, size_kb);
    ram_resource(dev, index++, base_kb, size_kb);

+	/* fsp_mem_base -> cbmem_top */
+	base_kb = top_of_ram / KiB;
+	size_kb = ((uintptr_t)cbmem_top() - top_of_ram) / KiB;
+	reserved_ram_resource(dev, index++, base_kb, size_kb);
+
    /*
     * FSP meomoy, CBMem regions are already added as reserved
     * Add TSEG and MESEG Regions as reserved memory