Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38461 )
Change subject: soc/intel/tigerlake: Update fsp params for Jasper Lake ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/38461/5/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_jsl.c:
https://review.coreboot.org/c/coreboot/+/38461/5/src/soc/intel/tigerlake/fsp... PS5, Line 4: 2020 2019-2020
https://review.coreboot.org/c/coreboot/+/38461/5/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:
https://review.coreboot.org/c/coreboot/+/38461/5/src/soc/intel/tigerlake/rom... PS5, Line 16: #include <assert.h> needed?
https://review.coreboot.org/c/coreboot/+/38461/5/src/soc/intel/tigerlake/rom... PS5, Line 19: #include <soc/gpio_soc_defs.h> : #include <soc/iomap.h> needed?
https://review.coreboot.org/c/coreboot/+/38461/5/src/soc/intel/tigerlake/rom... PS5, Line 57: for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { new line /* Pcie Root port configuration */
https://review.coreboot.org/c/coreboot/+/38461/5/src/soc/intel/tigerlake/rom... PS5, Line 108: /* MbHob */ : m_cfg->SkipMbpHob = 0; not needed.