[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Add FSP UPD for minimum assertion widths

[V Sowmya (Code Review)]

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43791 )

Change subject: soc/intel/jasperlake: Add FSP UPD for minimum assertion widths
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Patch Set 5:

(2 comments)

https://review.coreboot.org/c/coreboot/+/43791/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43791/4//COMMIT_MSG@9 
PS4, Line 9: Add the FSP UPD for the chipset minimum assertion width
> nit: Add the FSP UPDs for the PchPmPwrCycDur dependent sleep signal assertion widths

Since we are adding PchPmSlpSusMinAssert also here which is not PchPmPwrCycDur dependent sleep signal, i will retain as it is here.

https://review.coreboot.org/c/coreboot/+/43791/1/src/soc/intel/jasperlake/ch... 
File src/soc/intel/jasperlake/chip.h:

https://review.coreboot.org/c/coreboot/+/43791/1/src/soc/intel/jasperlake/ch... 
PS1, Line 344: 	 *  - PM_CFG.SLP_LAN_MIN_ASST_WDTH
> Could you elaborate on this question?

Done