Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36137 )
Change subject: soc/intel: skl,cnl,icl: consolidate ebda and memmap ......................................................................
Patch Set 26:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36137/25/src/soc/intel/apollolake/m... File src/soc/intel/apollolake/memmap.c:
https://review.coreboot.org/c/coreboot/+/36137/25/src/soc/intel/apollolake/m... PS25, Line 52: void fill_postcar_frame(struct postcar_frame *pcf) : { : uintptr_t top_of_ram; : : /* : * We need to make sure ramstage will be run cached. At this point exact : * location of ramstage in cbmem is not known. Instruct postcar to cache : * 16 megs under cbmem top which is a safe bet to cover ramstage. : */ : top_of_ram = (uintptr_t) cbmem_top(); : /* cbmem_top() needs to be at least 16 MiB aligned */ : assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); : postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB, : MTRR_TYPE_WRBACK); : : /* Cache the TSEG region */ : postcar_enable_tseg_cache(pcf); : }
Can you split this off in a separate patch? That would be trivial to review.
done in CB:36410