Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59393 )
Change subject: fsp: Change post codes to lower case ......................................................................
fsp: Change post codes to lower case
Signed-off-by: Sean Rhodes sean@starlabs.systems Change-Id: I65a83fcd69296f13c63329701ba9ce53f7cc2cb3 --- M src/drivers/intel/fsp1_1/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram.S 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/59393/1
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index e20d527..6a19b87 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -181,7 +181,7 @@ pushl %eax /* tsc[31:0] */
before_romstage: - post_code(0x2A) + post_code(0x2a)
/* Call bootblock_c_entry(uint64_t base_timestamp) */ call bootblock_c_entry diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index cac7854..1c905a4 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -295,7 +295,7 @@ #endif
before_carstage: - post_code(0x2A) + post_code(0x2a)
call bootblock_c_entry /* Never reached */