Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger.
Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74840
to look at the new patch set (#2).
Change subject: soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC ......................................................................
soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC
The 2*4 IO ports from 0xcf8 to 0xcff are used for the IO-based PCI config space access, so they wont be decoded to the LPC device and the devices below it, so split the subtractive IO range of the LPC device that those IO ports aren't covered by the subtractive IO regions of the LPC device.
TEST=The coreboot console output on mandolin now shows the two subtractive IO regions on the LPC device instead of the one that also covered the PCI config IO ports:
PCI: 00:14.3 resource base 0 size 0 align 0 gran 0 limit cf7 flags c0040100 index 10000000 PCI: 00:14.3 resource base d00 size 0 align 0 gran 0 limit fff flags c0040100 index 10000100
The contents of /proc/mem are still identical.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I67458dd14fa89d223e97c2410484c08654a6fab8 --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 36 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/74840/2