24 Jan
2020
24 Jan
'20
2:19 a.m.
Wonkyu Kim has uploaded a new patch set (#5) to the change originally created by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/38505 )
Change subject: mb/intel/tglrvp: Enable SATA ......................................................................
mb/intel/tglrvp: Enable SATA
Enable both SATA ports for TGLRVP.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/38505/5
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32
Gerrit-Change-Number: 38505
Gerrit-PatchSet: 5
Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com
Gerrit-Reviewer: Furquan Shaikh furquan@google.com
Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com
Gerrit-Reviewer: Raj Astekar raj.astekar@intel.com
Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com
Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com
Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com
Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net
Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com
Gerrit-CC: caveh jalali caveh@chromium.org
Gerrit-MessageType: newpatchset