Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50244 )
Change subject: soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers
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Patch Set 2:
(1 comment)
File src/soc/amd/picasso/include/soc/southbridge.h:
https://review.coreboot.org/c/coreboot/+/50244/comment/fdfde38a_1a20018a
PS2, Line 79: 32
Where in the datasheet did you find this?
see FCH::PM::EventStat and FCH::PM::EventEnable in the PPR #55570. No idea where the 28 is from; it just got copied over from Stoneyridge
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