Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43958 )
Change subject: soc/mediatek/mt8192: Add PLL and clock init support
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Patch Set 1:
(1 comment)
@jwerner, do you think it's fine to waive the 96-column for this file? I feel keeping the mux def in one line would improve readability.
https://review.coreboot.org/c/coreboot/+/43958/1/src/soc/mediatek/mt8192/pll...
File src/soc/mediatek/mt8192/pll.c:
https://review.coreboot.org/c/coreboot/+/43958/1/src/soc/mediatek/mt8192/pll...
PS1, Line 457: setbits32(&mtk_topckgen->clk_scp_cfg_0 , 0x3ff);
space prohibited before that ',' (ctx:WxW)
Please fix this
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Gerrit-Project: coreboot
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