[coreboot-gerrit] Change in coreboot[master]: [NOTFORMERGE_YET]soc/intel/xeon_sp/cpx: Hook up microcode update

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49082 )

Change subject: [NOTFORMERGE_YET]soc/intel/xeon_sp/cpx: Hook up microcode update
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Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/49082/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/49082/3//COMMIT_MSG@12 
PS3, Line 12: release.
The CPX-SP microcode update is definitely slowing down as the processor is approaching MP (Mass Production) status. To date, we get newer microcodes through Intel bi-weekly CPX-SP FSP releases. This model makes sense before CPX-SP reaches MP status.
After CPX-SP reaches MP status, we should switch to using microcode of publicly available, and merge in this patch.
After CPX-SP reaches MP status, Intel will also publish ME (ignite) binary and FSP binary to the community. Additional coreboot patches will be made to use those binaries. And then anyone in the industry could make fully functioning host firmware image for CPX-SP based server platform.