[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8183: improve the DRAMC runtime config flow

[Duan huayang (Code Review)]

Duan huayang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38490 )

Change subject: soc/mediatek/mt8183: improve the DRAMC runtime config flow
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Patch Set 3:

(3 comments)

https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/dra... 
File src/soc/mediatek/mt8183/dramc_pi_basic_api.c:

https://review.coreboot.org/c/coreboot/+/38490/1/src/soc/mediatek/mt8183/dra... 
PS1, Line 326: 		(0x7 << 22) | (0x3 << 14) | (0x1 << 19) | (0x1 << 21));
> I think it means this: […]

Done

https://review.coreboot.org/c/coreboot/+/38490/2/src/soc/mediatek/mt8183/dra... 
File src/soc/mediatek/mt8183/dramc_pi_basic_api.c:

https://review.coreboot.org/c/coreboot/+/38490/2/src/soc/mediatek/mt8183/dra... 
PS2, Line 350: size_t
> u8 (since all other code uses u8 for b)?

Done

https://review.coreboot.org/c/coreboot/+/38490/2/src/soc/mediatek/mt8183/dra... 
PS2, Line 362: clrsetbits32
> this has changed the logic (set 0x2 instead of 0x3). […]

will revert this unless change.