Subrata Banik has uploaded a new patch set (#3) to the change originally created by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/39117 )
Change subject: vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header file for Tiger Lake
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vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header file for Tiger Lake
Update FSP header file for Tiger Lake platform version 2457.
Add SerialIoUartAutoFlow, Enable8254ClockGating, Enable8254ClockGatingOnS3 UPD
Change-Id: Ib2a08ce73526fb0eb4e7c2a674af78c2913f0a08
Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com
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M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
1 file changed, 62 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/39117/3
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib2a08ce73526fb0eb4e7c2a674af78c2913f0a08
Gerrit-Change-Number: 39117
Gerrit-PatchSet: 3
Gerrit-Owner: Ronak Kanabar
ronak.kanabar@intel.com
Gerrit-Reviewer: Aamir Bohra
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Gerrit-Reviewer: Patrick Rudolph
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Gerrit-Reviewer: Ronak Kanabar
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Gerrit-Reviewer: Srinidhi N Kaushik
srinidhi.n.kaushik@intel.com
Gerrit-Reviewer: Subrata Banik
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Gerrit-Reviewer: Wonkyu Kim
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Gerrit-Reviewer: build bot (Jenkins)
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Gerrit-CC: Frans Hendriks
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Gerrit-CC: Paul Menzel
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Gerrit-MessageType: newpatchset
