Attention is currently required from: Nico Huber, Paul Menzel, Nicholas Chin, Swift Geek (Sebastian Grzywna), Elyes Haouas.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34826 )
Change subject: nb/intel/gm45: Wedge DDR2 SPD support in ......................................................................
Patch Set 15:
(3 comments)
File src/northbridge/intel/gm45/raminit.c:
https://review.coreboot.org/c/coreboot/+/34826/comment/12a7bdbf_dd4315f1 PS15, Line 232: test_dimm(sysinfo, dimm, 6, 0xff, 0x40
I think it's assuming that if the data width isn't 64 bits then it's probably 72 bits which would be […]
Seems likely, yes
https://review.coreboot.org/c/coreboot/+/34826/comment/8c8c6f96_f5e9cf60 PS15, Line 233: !test_dimm(sysinfo, dimm, 11, 0xff, 0x00)) : die("Chipset doesn't support ECC RAM\n");
if (dimm_info.flags.is_ecc) […]
Does gm45 code have dimm_info?
https://review.coreboot.org/c/coreboot/+/34826/comment/2e43ae54_276635f6 PS15, Line 334: typedef struct { : int dimm_mask; : struct spd_dimminfo { : unsigned int rows; : unsigned int cols; : unsigned int chip_capacity; : unsigned int banks; : unsigned int ranks; : unsigned int cas_latencies; : unsigned int tAAmin; : unsigned int tCKmin; : unsigned int width; : unsigned int tRAS; : unsigned int tRP; : unsigned int tRCD; : unsigned int tWR; : unsigned int page_size; : unsigned int raw_card; : } channel[2]; : } spdinfo_t;
[out of topic] […]
It's not needed in any other file.