[coreboot-gerrit] Change in coreboot[master]: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37213 )

Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
......................................................................

[TESTONLY]nb/intel/x4x: Cache cbmem in romstage

Probably not a good idea to avoid eviction in romstage.

TESTED: works fine on P5QL-EM.

Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/raminit.c
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37213/1

diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 2a54e24..6665eb0 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -27,6 +27,7 @@
    select CACHE_MRC_SETTINGS
    select PARALLEL_MP
    select C_ENVIRONMENT_BOOTBLOCK
+	select ROMSTAGE_CACHED_CBMEM

config CBFS_SIZE
    hex
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 8013af9..e8729fb 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -33,6 +33,7 @@
 #include <mrc_cache.h>
 #include <timestamp.h>
 #include <types.h>
+#include <cpu/x86/mtrr.h>

#include "iomap.h"
 #include "x4x.h"
@@ -718,6 +719,7 @@
    pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, reg8 | 1);
    printk(BIOS_DEBUG, "RAM initialization finished.\n");

+	setup_romstage_wb_cbmem_cache();
    cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME);
    if (!fast_boot)
    	mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION,