Naresh Solanki (naresh.solanki@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17839
-gerrit
commit 2bece926f37efc1bf9808db612880ec8a91c07e8 Author: Naresh G Solanki naresh.solanki@intel.com Date: Tue Dec 13 21:16:46 2016 +0530
x86: Configure premem cbmem console size
Sometime preram cbmem logs are truncated due to lack of space (default preram cbmem console size is 0xc00).
Provide Kconfig option to configure preram cbmem console size so that mainboard can configure it to required value.
Change-Id: I221d9170c547d41d8bd678a3a8b3bca6a76ccd2e Signed-off-by: Naresh G Solanki naresh.solanki@intel.com --- src/arch/x86/Kconfig | 6 ++++++ src/arch/x86/car.ld | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index cd5f8e5..6280024 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -118,6 +118,12 @@ config LATE_CBMEM_INIT early get_top_of_ram() call for romstage. CBMEM tables will be allocated late in ramstage, after PCI devices resources are known.
+config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xc00 + help + Increase this value if preram cbmem console is getting truncated + config PC80_SYSTEM bool default y if ARCH_X86 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index c221fb8..9236009 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -36,7 +36,7 @@ * in size. Therefore place them at the beginning .car.data section * so that multiple stages (romstage and verstage) have a consistent * link address of these shared objects. */ - PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) + PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)) _car_relocatable_data_start = .; /* The timestamp implementation relies on this storage to be around * after migration. One of the fields indicates not to use it as the