[coreboot-gerrit] Change in coreboot[master]: [WIP]soc/intel/tigerlake: Update C-state latencies

[Ravishankar Sarawadi (Code Review)]

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43316 )

Change subject: [WIP]soc/intel/tigerlake: Update C-state latencies
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[WIP]soc/intel/tigerlake: Update C-state latencies

Update newly recommended C-state latency values.

Signed-off-by: Ravi Sarawadi 
Change-Id: Ic1258ecbb355b94889b30d01bceca586525bbe5e
---
M src/soc/intel/tigerlake/include/soc/cpu.h
1 file changed, 5 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43316/1

diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h
index 28dfb38..47a41eb 100644
--- a/src/soc/intel/tigerlake/include/soc/cpu.h
+++ b/src/soc/intel/tigerlake/include/soc/cpu.h
@@ -7,11 +7,11 @@

/* Latency times in us */
 #define C1_LATENCY	1
-#define C6_LATENCY	127
-#define C7_LATENCY	253
-#define C8_LATENCY	260
-#define C9_LATENCY	487
-#define C10_LATENCY	1048
+#define C6_LATENCY	121
+#define C7_LATENCY	152
+#define C8_LATENCY	256
+#define C9_LATENCY	340
+#define C10_LATENCY	1034

/* Power in units of mW */
 #define C1_POWER	0x3e8