Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38988 )
Change subject: mainboard: Add new Ivy Bridge board ASUS P8Z77-M ......................................................................
Patch Set 11:
(5 comments)
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/Kconfig:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 29: config MAX_CPUS : int : default 8 already set in cpu/intel/model_206ax
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/cmos.layout:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 98: # gfx_uma_size (Intel IGP Video RAM size) : 7 0 32M : 7 1 64M : 7 2 96M : 7 3 128M : 7 4 160M : 7 5 192M : 7 6 224M : 7 7 256M : 7 8 288M : 7 9 320M : 7 10 352M : 7 11 384M : 7 12 416M : 7 13 448M : 7 14 480M : 7 15 512M : 7 16 544M : 7 17 576M : 7 18 608M : 7 19 640M : 7 20 672M : 7 21 704M : 7 22 736M : 7 23 768M : 7 24 800M : 7 25 832M : 7 26 864M : 7 27 896M : 7 28 928M : 7 29 960M : 7 30 992M From "Document Number: 326765-005Desktop 3rd Generation Intel®Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron®Processor FamilyDatasheet – Volume 2 of 2"
Encodings are as follows: 0h = 0 MB 1h = 32 MB 2h = 64 MB 3h = 96 MB 4h = 128 MB 5h = 160 MB 6h = 192 MB 7h = 224 MB 8h = 256 MB 9h = 288 MB Ah = 320 MB Bh = 352 MB Ch = 384 MB Dh = 416 MB Eh = 448 MB Fh = 480 MB 10h = 512 MB 11h = 1 GB
So the last part is not linear. 1G is not an option on sandybridge btw
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... File src/mainboard/asus/p8z77-m/early_init.c:
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 48: static const u8 register_values[] = {
I'd strongly recommend adding some comment here explaining this is done to save some bytes. Otherwise, people may be tempted to change this to align it with other boards.
I don't think it's worth it to save a few bytes here over using proper code.
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 89: /* This sequence enables early serial */ : SWITCH_TO, NCT6779D_SP1, : PNP_IDX_EN, 0, : PNP_IDX_IO0, CONFIG_TTYS0_BASE >> 8, : PNP_IDX_IO0 + 1, CONFIG_TTYS0_BASE & 0xff, : PNP_IDX_EN, 1, nuvoton_enable_serial()
https://review.coreboot.org/c/coreboot/+/38988/11/src/mainboard/asus/p8z77-m... PS11, Line 164: pei->max_ddr3_freq = 1600; /* 1333=Sandy; 1600=Ivy */ has a devicetree option "max_mem_clock_mhz" but it looks like some other boards also set this in C code.