Roja Rani Yarubandi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42095 )
Change subject: sc7180: Remove QcLib specific changes from CB UART ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG@17 PS1, Line 17: done the changes
ok will change
Done
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG@19 PS1, Line 19: in coreboot UART driver.
OK will update blobs version
Done
https://review.coreboot.org/c/coreboot/+/42095/1//COMMIT_MSG@20 PS1, Line 20:
Sorry, I'm still a bit confused about what this patch does and why. […]
This change is w.r.t the bug https://partnerissuetracker.corp.google.com/issues/153515979 , before QcLib fix we were using the hack to configure the clock to 7.3728MHz to maintain the div=4 as per the QcLib requirement(as it reconfigures UART registers to achieve 115200 baud). Now we have QcLib fix in place, so we removed the hack.
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... File src/soc/qualcomm/sc7180/qupv3_config.c:
https://review.coreboot.org/c/coreboot/+/42095/1/src/soc/qualcomm/sc7180/qup... PS1, Line 55: if (protocol != SE_PROTOCOL_UART) {
How is the QUP clock configured now if you just take this out? Shouldn't we still call […]
The source clock is assumed as 19.2MHz, and for this no need to call clock_configure_qup(). We are following the same for all (SPI, UART, I2C) drivers. You want this clock_configure_qup() to be called specifically for UART driver?