[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training

[Subrata Banik (Code Review)]

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Vikrant L Jadeja.

Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email )

Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training
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Patch Set 15:

(1 comment)

File src/soc/intel/pantherlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/85454/comment/affc0982_b4a8030e?usp... :
PS11, Line 375:
> Thank you for the detailed information. We will take it into consideration once FSP provides a mechanism that allows us to request that the VGA not be disabled. Currently, `VgaInitControl` is implemented as a simple Boolean value. It is unclear whether it will be converted back to a bit field, or if an additional UPD will be provided to manage this request.

note. this is not for CrOS usecase but for other mainboards in future. Therefore, i believe we have some time to enable non-cros devices