build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35040 )
Change subject: soc/intel/common/block: Provide mmc.c for setting dll registers. ......................................................................
Patch Set 3:
(36 comments)
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 425: /* [14:8] DDR mode Number of dealy elements.Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 426: * [6:0] SDR mode Number of dealy elements.Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 427: */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 428: uint32_t emmc_tx_cmd_cntl; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 428: uint32_t emmc_tx_cmd_cntl; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 430: /* [14:8] HS400 mode Number of dealy elements.Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 431: * [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 432: */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 433: uint32_t emmc_tx_data_cntl1; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 433: uint32_t emmc_tx_data_cntl1; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 435: /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 436: * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 437: * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 438: * [6:0] SDR12/Compatibility mode Number of dealy elements. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 439: * Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 440: */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 441: uint32_t emmc_tx_data_cntl2; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 441: uint32_t emmc_tx_data_cntl2; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 443: /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 444: * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 445: * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 446: * [6:0] SDR12/Compatibility mode Number of dealy elements. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 447: * Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 448: */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 449: uint32_t emmc_rx_cmd_data_cntl1; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 449: uint32_t emmc_rx_cmd_data_cntl1; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 451: /* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 452: * [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 453: */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 454: uint32_t emmc_rx_strobe_cntl; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 454: uint32_t emmc_rx_strobe_cntl; please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 456: /* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 457: * [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec. code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 458: */ code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 459: uint32_t emmc_rx_cmd_data_cntl2; code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/35040/3/src/soc/intel/cannonlake/ch... PS3, Line 459: uint32_t emmc_rx_cmd_data_cntl2; please, no spaces at the start of a line