Martin Roth (gaumless@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6364
-gerrit
commit cdc1a2285c0616b6a43b716a5439083c0c2fb496 Author: Martin Roth martin.roth@se-eng.com Date: Fri Jul 25 14:39:05 2014 -0600
payloads/external/SeaBIOS: Allow setting buffers below 0xC0000
Add the option to coreboot to set the SeaBIOS buffers below 0xC0000. This is a requirement on the Intel Rangeley processor because it is designed so that only the processor can write the higher memory areas. This prevents USB and SATA from bus-mastering into the buffers when they're set in the typical 0xE0000 area.
This will be set to Y unless defaulted to N by the mainboard or chipset.
Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak
Change-Id: I15638605d1c66a2277d4b852796db89978551a34 Signed-off-by: Martin Roth martin.roth@se-eng.com --- payloads/external/SeaBIOS/Makefile.inc | 3 +++ src/Kconfig | 13 +++++++++++++ src/arch/x86/Makefile.inc | 1 + src/mainboard/intel/mohonpeak/Kconfig | 8 ++++++++ 4 files changed, 25 insertions(+)
diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 97f9d56..21bc9a7 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -31,6 +31,9 @@ ifeq ($(CONFIG_CONSOLE_SERIAL),y) else echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config endif +ifneq ($(CONFIG_SEABIOS_MALLOC_UPPERMEMORY),y) + echo "# CONFIG_MALLOC_UPPERMEMORY is not set" >> $(OUT)/seabios/.config +endif ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config endif diff --git a/src/Kconfig b/src/Kconfig index 97a4799..443732a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -623,6 +623,19 @@ config SEABIOS_THREAD_OPTIONROMS variations during option ROM code execution. It is not known if all option ROMs will behave properly with this option.
+config SEABIOS_MALLOC_UPPERMEMORY + bool + default y + depends on PAYLOAD_SEABIOS + help + Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal + "low memory" allocations. If this is not selected, the memory is + instead allocated from the "9-segment" (0x90000-0xa0000). + This is not typically needed, but may be required on some platforms + to allow USB and SATA buffers to be written correctly by the + hardware. In general, if this is desired, the option will be + set to 'N' by the chipset Kconfig. + choice prompt "GRUB2 version" default GRUB2_MASTER diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 036dc1a..aa058c0 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -351,6 +351,7 @@ seabios: CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \ + CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) \ OUT=$(abspath $(obj)) IASL="$(IASL)"
filo: diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index edf1fb8..eb97663 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -96,4 +96,12 @@ config UART_FOR_CONSOLE help The Mohon Peak board uses COM2 (2f8) for the serial console.
+config SEABIOS_MALLOC_UPPERMEMORY + bool + default n + help + The Avoton/Rangeley chip does not allow devices to write into the 0xe000 + segment. This means that USB/SATA devices will not work in SeaBIOS unless + we put the SeaBIOS buffer area down in the 0x9000 segment. + endif # BOARD_INTEL_MOHONPEAK