Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39460
to look at the new patch set (#2).
Change subject: mainboard: Set Tiger Lake platforms to have retimer config Aux orientation ......................................................................
mainboard: Set Tiger Lake platforms to have retimer config Aux orientation
In order to create a working baseline all ports are being set to have retimers. Setting the TcssAuxOri UPD to 0 in order for the SoC to not misconfigure the ports. Volteer will need some additional changes after this is implemented to account for ports that do not have a retimers this setting is in the process of being documented in the TGL EDS and we can update once it is fully understood what this setting is changing on the SOC side.
BUG=b:145943811 BRANCH=none TEST=Boot to OS and check TypeC port1 Display, Connecting type-c display should work regardless of type-c cable orientation.
Change-Id: I29eb0513299126ad8d1ee11ded2c771f28ad13f3 Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 3 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/39460/2