Hello Patrick Rudolph, David Guckian, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34928
to look at the new patch set (#7).
Change subject: intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor ......................................................................
intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor
Remove cases of __PRE_RAM__ and other preprocessor guards.
Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/drivers/intel/fsp1_0/fastboot_cache.c M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/baytrail/include/soc/ramstage.h M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/tsc_freq.c M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/gpio.c M src/soc/intel/fsp_baytrail/include/soc/baytrail.h M src/soc/intel/fsp_baytrail/include/soc/pmc.h M src/soc/intel/fsp_baytrail/include/soc/ramstage.h M src/soc/intel/fsp_baytrail/include/soc/romstage.h M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_baytrail/tsc_freq.c M src/southbridge/intel/fsp_rangeley/acpi.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/romstage.h M src/southbridge/intel/fsp_rangeley/sata.c M src/southbridge/intel/fsp_rangeley/soc.h M src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c 25 files changed, 40 insertions(+), 132 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/34928/7