Attention is currently required from: Stefan Reinauer.
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68186 )
Change subject: util/inteltool: Add support for (non-ULT) Broadwell ......................................................................
util/inteltool: Add support for (non-ULT) Broadwell
Add support for traditional (non-ULT) Broadwell.
Change-Id: Ibe0ed9badd580e28060fe8df14a01352d4c1e11e Signed-off-by: Angel Pons th3fanbus@gmail.com --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/memory.c M util/inteltool/pcie.c 4 files changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/68186/1
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 6b9ff13..cc4454a 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -107,6 +107,10 @@ "4th generation (Haswell family) Core Processor ULT" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U, "5th generation (Broadwell family) Core Processor ULT" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D, + "5th generation (Broadwell family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M, + "5th generation (Broadwell family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M, "6th generation (Skylake-H family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 0689438..1968ee9 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -329,6 +329,8 @@ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */ #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */ +#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D 0x1610 /* Broadwell (Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M 0x1614 /* Broadwell (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2 0x190f /* Skylake (Desktop) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U 0x1904 /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y 0x190c /* Skylake (Mobile) */ diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 36d1197..a536d39 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -206,6 +206,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index d392c28..fb29d32 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -250,6 +250,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: @@ -369,6 +371,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: dmibar_phys = pci_read_long(nb, 0x68); dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ @@ -496,6 +500,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: