20 Jul
2021
20 Jul
'21
12:11 a.m.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/13070 )
Change subject: intel/skylake: Thermal Design Power PL1 and PL2 Config Changes ......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/13070/comment/3589ea0d_6f13c206 PS2, Line 10: Disable PL1 configuration via MMIO register.
Stumbled over this in the code and now I wonder: why was this […]
The information might be in the bug report:
BUG=chrome-os-partner:49292
Though I do not know, how to access that information.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I10742f91cc7179de1482d42392338976e8082afe
Gerrit-Change-Number: 13070
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Gerrit-Reviewer: Martin Roth martinroth@google.com
Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com
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