Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40523 )
Change subject: soc/xeon_sp: Read PPIN MSR and save to an array for each CPU ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40523/5/src/soc/intel/xeon_sp/skx/c... File src/soc/intel/xeon_sp/skx/cpu.c:
https://review.coreboot.org/c/coreboot/+/40523/5/src/soc/intel/xeon_sp/skx/c... PS5, Line 75: /* If socket_index is 0 then all PPIN have been saved. */
I wonder if this logic is over complicated. […]
You are right, but I can't find a way to only read the MSR on a core in the 2nd socket without running on all cores. mp_run_on_aps() is similar to this need but it still runs on all APs. I think FSP should be able to provide the PPIN for each socket, or maybe until there's a more ideal way we only read socket0 PPIN?