Attention is currently required from: Felix Singer, Christian Walter, Angel Pons, Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 )
Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ......................................................................
Patch Set 66:
(5 comments)
File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/37441/comment/d41238e8_03ceb5ff PS65, Line 16: device pci 14.2 on end
I've no idea of what this is
Done
File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/37441/comment/feaf9559_4a22d758 PS64, Line 6:
What is it necessary for?
*poke*
https://review.coreboot.org/c/coreboot/+/37441/comment/1933f33f_535e4284 PS64, Line 29: register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80" : register "PcieClkSrcUsage[6]" = "0x80" : register "PcieClkSrcUsage[7]" = "0x80" : register "PcieClkSrcUsage[8]" = "0x80" : register "PcieClkSrcUsage[9]" = "0x80" : register "PcieClkSrcUsage[10]" = "0x80" : register "PcieClkSrcUsage[11]" = "0x80" : register "PcieClkSrcUsage[12]" = "0x80" : register "PcieClkSrcUsage[13]" = "0x80" : register "PcieClkSrcUsage[14]" = "0x80" : register "PcieClkSrcUsage[15]" = "0x80" : : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : register "PcieClkSrcClkReq[6]" = "6" : register "PcieClkSrcClkReq[7]" = "7" : register "PcieClkSrcClkReq[8]" = "8" : register "PcieClkSrcClkReq[9]" = "9" : register "PcieClkSrcClkReq[10]" = "10" : register "PcieClkSrcClkReq[11]" = "11" : register "PcieClkSrcClkReq[12]" = "12" : register "PcieClkSrcClkReq[13]" = "13" : register "PcieClkSrcClkReq[14]" = "14" : register "PcieClkSrcClkReq[15]" = "15"
Given the non-linear mapping between PCIe RPs and clksrc/clkreq pins, it is not trivial to determine […]
Ack
https://review.coreboot.org/c/coreboot/+/37441/comment/c9a2061e_b0cee6ba PS64, Line 121: device pci 1d.0 on end # PCIE x4
add smbios info?
Done, and this is actually another NVMe slot
File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/37441/comment/b46f23e2_e1d5065a PS65, Line 29: register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80" : register "PcieClkSrcUsage[6]" = "0x80" : register "PcieClkSrcUsage[7]" = "0x80" : register "PcieClkSrcUsage[8]" = "0x80" : register "PcieClkSrcUsage[9]" = "0x80" : register "PcieClkSrcUsage[10]" = "0x80" : register "PcieClkSrcUsage[11]" = "0x80" : register "PcieClkSrcUsage[12]" = "0x80" : register "PcieClkSrcUsage[13]" = "0x80" : register "PcieClkSrcUsage[14]" = "0x80" : register "PcieClkSrcUsage[15]" = "0x80" : : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : register "PcieClkSrcClkReq[6]" = "6" : register "PcieClkSrcClkReq[7]" = "7" : register "PcieClkSrcClkReq[8]" = "8" : register "PcieClkSrcClkReq[9]" = "9" : register "PcieClkSrcClkReq[10]" = "10" : register "PcieClkSrcClkReq[11]" = "11" : register "PcieClkSrcClkReq[12]" = "12" : register "PcieClkSrcClkReq[13]" = "13" : register "PcieClkSrcClkReq[14]" = "14" : register "PcieClkSrcClkReq[15]" = "15" :
Looks like the clksrc/clkreq mapping isn't linear.
Since none of the ports use CLKREQ# right now, I'll drop that and keep the CLKSRCs free-running.