Attention is currently required from: Felix Singer, Christian Walter, Angel Pons, Michael Niewöhner.

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5 comments:

• File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb:

  • Patch Set #65, Line 16: device pci 14.2 on end

    I've no idea of what this is

    Done

• File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb:

  • Patch Set #64, Line 6:

    What is it necessary for?

    *poke*

  • Patch Set #64, Line 29:

    	register "PcieClkSrcUsage[0]" = "0x80"
    	register "PcieClkSrcUsage[1]" = "0x80"
    	register "PcieClkSrcUsage[2]" = "0x80"
    	register "PcieClkSrcUsage[3]" = "0x80"
    	register "PcieClkSrcUsage[4]" = "0x80"
    	register "PcieClkSrcUsage[5]" = "0x80"
    	register "PcieClkSrcUsage[6]" = "0x80"
    	register "PcieClkSrcUsage[7]" = "0x80"
    	register "PcieClkSrcUsage[8]" = "0x80"
    	register "PcieClkSrcUsage[9]" = "0x80"
    	register "PcieClkSrcUsage[10]" = "0x80"
    	register "PcieClkSrcUsage[11]" = "0x80"
    	register "PcieClkSrcUsage[12]" = "0x80"
    	register "PcieClkSrcUsage[13]" = "0x80"
    	register "PcieClkSrcUsage[14]" = "0x80"
    	register "PcieClkSrcUsage[15]" = "0x80"
    
    	register "PcieClkSrcClkReq[0]" = "0"
    	register "PcieClkSrcClkReq[1]" = "1"
    	register "PcieClkSrcClkReq[2]" = "2"
    	register "PcieClkSrcClkReq[3]" = "3"
    	register "PcieClkSrcClkReq[4]" = "4"
    	register "PcieClkSrcClkReq[5]" = "5"
    	register "PcieClkSrcClkReq[6]" = "6"
    	register "PcieClkSrcClkReq[7]" = "7"
    	register "PcieClkSrcClkReq[8]" = "8"
    	register "PcieClkSrcClkReq[9]" = "9"
    	register "PcieClkSrcClkReq[10]" = "10"
    	register "PcieClkSrcClkReq[11]" = "11"
    	register "PcieClkSrcClkReq[12]" = "12"
    	register "PcieClkSrcClkReq[13]" = "13"
    	register "PcieClkSrcClkReq[14]" = "14"
    	register "PcieClkSrcClkReq[15]" = "15"
    

    Given the non-linear mapping between PCIe RPs and clksrc/clkreq pins, it is not trivial to determine […]

    Ack

  • Patch Set #64, Line 121: device pci 1d.0 on end # PCIE x4

    add smbios info?

    Done, and this is actually another NVMe slot

• File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb:

  • Patch Set #65, Line 29:

    	register "PcieClkSrcUsage[0]" = "0x80"
    	register "PcieClkSrcUsage[1]" = "0x80"
    	register "PcieClkSrcUsage[2]" = "0x80"
    	register "PcieClkSrcUsage[3]" = "0x80"
    	register "PcieClkSrcUsage[4]" = "0x80"
    	register "PcieClkSrcUsage[5]" = "0x80"
    	register "PcieClkSrcUsage[6]" = "0x80"
    	register "PcieClkSrcUsage[7]" = "0x80"
    	register "PcieClkSrcUsage[8]" = "0x80"
    	register "PcieClkSrcUsage[9]" = "0x80"
    	register "PcieClkSrcUsage[10]" = "0x80"
    	register "PcieClkSrcUsage[11]" = "0x80"
    	register "PcieClkSrcUsage[12]" = "0x80"
    	register "PcieClkSrcUsage[13]" = "0x80"
    	register "PcieClkSrcUsage[14]" = "0x80"
    	register "PcieClkSrcUsage[15]" = "0x80"
    
    	register "PcieClkSrcClkReq[0]" = "0"
    	register "PcieClkSrcClkReq[1]" = "1"
    	register "PcieClkSrcClkReq[2]" = "2"
    	register "PcieClkSrcClkReq[3]" = "3"
    	register "PcieClkSrcClkReq[4]" = "4"
    	register "PcieClkSrcClkReq[5]" = "5"
    	register "PcieClkSrcClkReq[6]" = "6"
    	register "PcieClkSrcClkReq[7]" = "7"
    	register "PcieClkSrcClkReq[8]" = "8"
    	register "PcieClkSrcClkReq[9]" = "9"
    	register "PcieClkSrcClkReq[10]" = "10"
    	register "PcieClkSrcClkReq[11]" = "11"
    	register "PcieClkSrcClkReq[12]" = "12"
    	register "PcieClkSrcClkReq[13]" = "13"
    	register "PcieClkSrcClkReq[14]" = "14"
    	register "PcieClkSrcClkReq[15]" = "15"
    
    

    Looks like the clksrc/clkreq mapping isn't linear.

    Since none of the ports use CLKREQ# right now, I'll drop that and keep the CLKSRCs free-running.

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