Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47286 )
Change subject: soc/intel/jasperlake: Enable Intel FIVR RFI settings ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47286/2/src/soc/intel/jasperlake/ch... File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/47286/2/src/soc/intel/jasperlake/ch... PS2, Line 360: Each Range is translated to an encoded value for FIVR register. 0.5% = 0, 1% : * = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
I think this can change to the FSP comment: […]
Ack
https://review.coreboot.org/c/coreboot/+/47286/2/src/soc/intel/jasperlake/fs... File src/soc/intel/jasperlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/47286/2/src/soc/intel/jasperlake/fs... PS2, Line 220: params->FivrRfiFrequency = config->FivrRfiFrequency;
Just checked, both are 0 in FSP.
Yes Eric/Tim, Since FSP defaults are 0, we can safely fill it from devicetree. If someone doesn't set value from devicetree then also, config value will be 0 which aligns with FSP default.