[coreboot-gerrit] [M] Change in coreboot[master]: drivers/intel/gma: Hook up libgfxinit in romstage

[Angel Pons (Code Review)]

Attention is currently required from: Bora Guvendik, Zhixing Ma, Anil Kumar K, Hannah Williams, Cliff Huang, Tarun Tuli, Nico Huber, Michał Żygowski, Jérémy Compostella, Paul Menzel, Arthur Heymans.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70276 )

Change subject: drivers/intel/gma: Hook up libgfxinit in romstage
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Patch Set 19:

(2 comments)

File src/drivers/intel/gma/Kconfig:

https://review.coreboot.org/c/coreboot/+/70276/comment/77614eea_b0dfd373 
PS13, Line 95: SOC_INTEL_ALDERLAKE
> Agreed.  Suggest separating cleanup of existing block from this patch train though as out of scope.

Let's keep it like this for now.

File src/drivers/intel/gma/Kconfig:

https://review.coreboot.org/c/coreboot/+/70276/comment/cc048285_350f6fbb 
PS15, Line 105: If
              : 	  libgfxinit is used for both romstage and ramstage this
              : 	  address should be the same than the one allocated by the PCI
              : 	  resource allocator in ramstage.
> The issue is that libhwbase decides of which driver to build and use at build time based on HWBASE_S […]

For now, you can tell coreboot to report BAR0 as a fixed resource. This avoids surprises later on in case something regarding allocation changes, e.g. PCIe bridges at 00.01.x being populated or not.

https://gist.github.com/Th3Fanbus/2f3c65aaccc0e1002a852951eb6d682d should do the trick. A long-term solution could be to replace the `HWBASE_STATIC_MMIO` and `HWBASE_DYNAMIC_MMIO` Kconfig options with stage-dependent implementations of some function. For instance, have a function that returns the base address; the romstage implementation returns a fixed base address and the ramstage implementation reads the value from the PCI config space registers.