[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP]

[Surendranath R Gurivireddy (Code Review)]

Surendranath R Gurivireddy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36519 )

Change subject: soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP]
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36519/3/src/soc/intel/cannonlake/fs... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/36519/3/src/soc/intel/cannonlake/fs... 
PS3, Line 277: 	params->PchUsb2PhySusPgEnable = 0;
> IMO this is just a proof-of-concept patch and not something we could use for a production device.

Verification of the patch is still in progress to assess the power impact.
This change is done based on the Intel's recommendation (Sighting is attached in the partner issue_
As suggested, added flag in the device tree and set to 0 only for WHL platforms