Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33129 )
Change subject: soc/intel/cannonlake: set temperature threshold for PCH Thermal Sensor ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/33129/5/src/soc/intel/cannonlake/th... File src/soc/intel/cannonlake/thermal.c:
https://review.coreboot.org/c/coreboot/+/33129/5/src/soc/intel/cannonlake/th... PS5, Line 31: trip_temp This macro should not make assumptions about variable name. It would be better to define this : #define GET_LTT_VALUE(v) ((v) + 50) * 2)
https://review.coreboot.org/c/coreboot/+/33129/5/src/soc/intel/cannonlake/th... PS5, Line 98: if (!thermalbar) {
You either don't understand why it's 0 or you don't care. […]
You will need something like this for hatch:
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 9a9125396c3..dffb3d66c78 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -112,7 +112,7 @@ chip soc/intel/cannonlake device pci 02.0 on end # Integrated Graphics Device device pci 04.0 off end # SA Thermal device device pci 05.0 off end # SA IPU - device pci 12.0 off end # Thermal Subsystem + device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on