[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Fix source clock check condition fo...

[Cliff Huang (Code Review)]

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73889 )

Change subject: soc/intel/common/block/pcie/rtd3: Fix source clock check condition for PM method
......................................................................

soc/intel/common/block/pcie/rtd3: Fix source clock check condition for PM method

If srcclk_pin is set to -1, then the clock will not be disabled in D3.
Therefore, clock source gating method should not be generated.

BUG=b:271003060
BRANCH=firmware-brya-14505.B
TEST=Boot to OS and check that rtd3 ACPI etnries are generated as expected

Signed-off-by: Cliff Huang 
Change-Id: Ia831b8fd17572cc35765bd226d1db470f12ddd41
---
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
1 file changed, 20 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/73889/1

diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c
index 1519e6f..b98606a 100644
--- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c
+++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c
@@ -401,9 +401,10 @@
    		return;
    	}
    }
-	if (config->srcclk_pin == 0) {
+	if (config->srcclk_pin == -1) {
    	if (config->ext_pm_support & ACPI_PCIE_RP_EMIT_SRCK) {
-			printk(BIOS_ERR, "%s: Can not export SRCK method\n", __func__);
+			printk(BIOS_ERR, "%s: Can not export SRCK method since clock source gating is not enabled\n",
+				__func__);
    		return;
    	}
    }