[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39459 )

Change subject: soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3
......................................................................

soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3

FSP UPD TcssAuxOri is used for setting the IOM_TYPEC_SW_CONFIGURATION_3.
Configure TcssAuxOri to retimer enabled on the port 2 Type-C port.
This setting informs the SoC that a retimer is taking care of SBU
orientation therefore it does not need to do any flipping.

The IOM_TYPEC_SW_CONFIGURATION_3 is a bitfield that controls the aux
orientation settings for the Type-C ports. The TGL EDS describes this
setting and what each bit represents.

Reference section 3.6.5 in TGL EDS #575681
BUG=b:145943811
BRANCH=none
TEST=Boot to OS and check Type-C port1 Display on volteer,
Connecting Type-C display should work regardless of Type-C cable
orientation.

Change-Id: Iae356113cbdc72983f800060b1ebebe3c66b9daf
Signed-off-by: Brandon Breitenstein 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39459
Reviewed-by: Caveh Jalali 
Reviewed-by: Wonkyu Kim 
Reviewed-by: Nick Vaccaro 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
2 files changed, 10 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved
  Caveh Jalali: Looks good to me, but someone else must approve
  Wonkyu Kim: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 1d4bd5f..64c13ce 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -232,6 +232,15 @@
    uint8_t TcssXdciEn;

/*
+	 * SOC Aux orientation override:
+	 * This is a bitfield that corresponds to up to 4 TCSS ports on TGL.
+	 * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC.
+	 * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines
+	 * on the motherboard.
+	 */
+	uint16_t TcssAuxOri;
+
+	/*
     * Override GPIO PM configuration:
     * 0: Use FSP default GPIO PM program,
     * 1: coreboot to override GPIO PM program
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index a8be407..8e9787b 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -104,6 +104,7 @@
    else
    	params->PeiGraphicsPeimInit = 0;

+	params->TcssAuxOri = config->TcssAuxOri;
    for (i = 0; i < 8; i++)
    	params->IomTypeCPortPadCfg[i] = 0x09000000;