EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config
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Patch Set 25:
(2 comments)
@Furquan, waiting for your helper 😊
https://review.coreboot.org/c/coreboot/+/48340/24/src/soc/intel/alderlake/ro...
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/24/src/soc/intel/alderlake/ro...
PS24, Line 23: pcie_clk_src_usage
suggestion: `convert_clk_src_to_fsp`
Done
https://review.coreboot.org/c/coreboot/+/48340/24/src/soc/intel/alderlake/ro...
PS24, Line 153: !is_dev_enabled(dev) ? 0
: : pcie_rp_init(m_cfg, CPU_PCIE_RP, config->cpu_pcie_rp, CONFIG_MAX_ROOT_PORTS);
I am waiting for Intel answer, still not clear CPU PCIE only relay on this port or not... […]
Done
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Gerrit-Change-Number: 48340
Gerrit-PatchSet: 25
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Gerrit-Reviewer: Furquan Shaikh
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