V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43793 )
Change subject: mb/intel/jslrvp: Update the sleep assertion widths and Power Cycle Duration ......................................................................
mb/intel/jslrvp: Update the sleep assertion widths and Power Cycle Duration
This patch updates the SLP_X assertion width and Power Cycle Duration for the Japerlake RVP.
BUG=b:159104150
Change-Id: Ie2a8d959d7ebbf9c24f8c4e8d5c68b70e0ac5708 Signed-off-by: V Sowmya v.sowmya@intel.com --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb 1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/43793/1
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 616e35c..8b39d51 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -154,6 +154,20 @@ }, }"
+ /* Set the minimum assertion width */ + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "3" # 1s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device