[coreboot-gerrit] Change in coreboot[master]: soc/intel/*: only enable PM Timer emulation if the PM Timer is disabled

[Michael Niewöhner (Code Review)]

Attention is currently required from:  Felix Singer, Lance Zhao, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Angel Pons, Subrata Banik, Patrick Rudolph.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57930 )

Change subject: soc/intel/*: only enable PM Timer emulation if the PM Timer is disabled
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Patch Set 4:

(1 comment)

Patchset:

PS4: 
We already had a discussion (CB:45000) on that topic but I need to bring that up once again.

AIUI timer emulation redirects (traps) all read/writes to the ACPI timer to the emulation. uCode emulates everything except a) TCO timer, which does not work without the hw timer and b) TMR_STS, which is used to generate timer overflow interrupts.

When both HW timer and uCode timer are enabled the OS/OSPM can never use the hw timer. However, when the TCO gets used and for some reason TMR_STS generates an interrupt, I have no idea what happens then. I don't even know if that's possible.

My suggestion is to disable timer emulation when the hw timer is present/enabled, since having both does not have any advantage.